Method of manufacturing double diffused MOSFET with potential biases
September 25, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTrench isolated transistors in semiconductor films MOS Semiconductor device and method of manufacturing the same Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer Process for forming MOS transistor with buried oxide regions for insulation Sidewall channel stop process Buried interconnect for silicon on insulator structure High voltage depletion mode MOS power field effect transistor Silicon semiconductor substrate with an insulating layer embedded therein and method for forming the same Double diffused mosfet with potential biases Patent #: 4884116 InventorApplicationNo. 412149 filed on 09/25/1989US Classes:438/295, Total dielectric isolation257/E21.32, Of silicon on insulator (SOI) (EPO)257/E21.567, Using bonding technique (EPO)257/E27.026, Integrated circuit having a three-dimensional layout (EPO)257/E29.261, With at least part of active region on insulating substrate (e.g., lateral DMOS in oxide isolated well) (EPO)257/E29.275, With multiple gates (EPO)257/E29.279, Asymmetrical source and drain regions (EPO)257/E29.281, For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)257/E29.286, Monocrystalline only (EPO)438/268, Vertical channel438/273, Having integral short of source and base regions438/455BONDING OF PLURAL SEMICONDUCTOR SUBSTRATESExaminersPrimary: Hearn, Brian E.Assistant: Quach, T. N. Attorney, Agent or FirmInternational ClassH01L 021/336Foreign Application Priority Data1986-12-20 JPAbstractFirst and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with each other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential. In this way, it is possible to improve the yield voltage characteristics between the first semiconductor region, which does not form any element, and the back gate region. The insulating region which electrically isolates the first and second semiconductor regions from each other, is formed by bonding together first and second silicon oxide films on surfaces of the first and second single crystal silicon substrates. Therefore, the process of manufacture is simplified.Other References
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