System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch
October 9, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3718912 Cooperative-word linear array parallel processor Instruction altering system Instruction execution modification mechanism for time slice controlled data processors Instruction set modifier register Data processing apparatus having op-code extension register Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element Programmable interconnection chip for computer system functional modules Polynomial vector arithmetic operation control system InventorsApplicationNo. 595720 filed on 10/09/1990US Classes:710/317, Crossbar708/524Multiple parallel operationsExaminersPrimary: Lee, Thomas C.Attorney, Agent or FirmInternational ClassG06F 015/80Foreign Application Priority Data1988-01-13 NLAbstractA data processor system having at least one arithmetic/logic processor element and at least one memory processor element which can be coupled in circuit using a crossbar switch. The arithmetic/logic processor element is provided with an ALU and a program memory. The ALU has an input for instructions. The instructions can be made up of data from the program memory and data from the crossbar switch via a channel specifically present for the purpose.Other References
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