Patent ReferencesLateral confinement of charge carriers in a multiple quantum well structure Double heterojunction semiconductor device with injector Heterojunction field effect transistor Floating gate memories Patent #: 4905063 InventorsAssigneeApplicationNo. 469995 filed on 01/25/1990US Classes:257/192, Field effect transistor257/278, With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit)257/280, With Schottky gate257/287, With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)257/513, Vertical walled groove257/E29.316, Programmable transistor (e.g., with charge-trapping quantum well) (EPO)257/E29.317With Schottky gate (EPO)ExaminersPrimary: James, Andrew J.Assistant: Van Ngo, Ngan Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/161H01L 029/80 H01L 029/34 AbstractA layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.Other References
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