U.S. patents available from 1976 to present.
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Multi-layer semiconductor device

Patent 5051865 Issued on September 24, 1991. Estimated Expiration Date: Icon_subject March 11, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3243660

3704455

3705332

Cooling system for multiwafer high density circuit
Patent #: 4283754
Issued on: 08/11/1981
Inventor: Parks

Stacked semiconductor device with sloping sides
Patent #: 4500905
Issued on: 02/19/1985
Inventor: Shibata

Interconnected multiple circuit module
Patent #: 4514784
Issued on: 04/30/1985
Inventor: Williams ,   et al.

Electronic circuit interconnection system
Patent #: 4546406
Issued on: 10/08/1985
Inventor: Spinelli ,   et al.

Circuit module with enhanced heat transfer and distribution
Patent #: 4628407
Issued on: 12/09/1986
Inventor: August ,   et al.

Multichip thin film module Patent #: 4698662
Issued on: 10/06/1987
Inventor: Young ,   et al.

Inventor

Assignee

Application

No. 667257 filed on 03/11/1991

US Classes:

361/718, For integrated circuit257/686, Stacked arrangement257/712, With provision for cooling the housing or its contents257/E23.101, Selection of materials, or shaping, to facilitate cooling or heating, e.g., heat sinks (EPO)257/E25.013, Stacked arrangements of devices (EPO)361/708Specific chemical compound or element

Examiners

Primary: Williams, Howard L.

Attorney, Agent or Firm

Foreign Patent References

  • 1599169 FR. 08/13/1970
  • 2124319 FR. 09/13/1972
  • 56191096 JP 05/13/1983
  • 61-18164 JP 01/13/1986
  • 1083200 GB. 09/13/1967
  • 1212279 GB. 11/13/1970

International Class

H01L 023/34

Foreign Application Priority Data

1985-06-17 JP

Abstract

A multi-layer semiconductor device which includes a stacked wafer body having a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween. An end of the heat sink plate of each set of wafers is exposed at at least one of the side surfaces of the stacked wafer body.An intermediate connecting circuit is provided for connecting circuits in each of the sets of two semiconductors wafers, the intermediate connecting circuit is provided on at least one side surface other than the surface at which the ends of the heat sink plate are exposed.

Other References

  • IBM Technical Disclosure Bulletin vol. 23, No. 11, Apr. 1981, p. 4835 "Stacked Thermally Enhanced High Package Density Module", Marks
  • PCT International Publication No. WO 85/02283, PCT/US83/01750
  • Patent Abstracts of Japan, vol. 10, No. 168 (E-411) [2224], Jun. 14, 1986 & JP-A-61 18 164 (Mitsubishi Denki K.K.) 27-01-198
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