U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of manufacturing semiconductor memory device

Patent 5049516 Issued on September 17, 1991. Estimated Expiration Date: Icon_subject December 15, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Nonvolatile semiconductor memory device and method of its manufacture
Patent #: 4307411
Issued on: 12/22/1981
Inventor: Carnes ,   et al.

Semiconductor memory device
Patent #: 4355375
Issued on: 10/19/1982
Inventor: Arakawa

Electrically alterable, nonvolatile floating gate memory device
Patent #: 4417264
Issued on: 11/22/1983
Inventor: Angle

Non-volatile programmable integrated semiconductor memory cell
Patent #: 4425631
Issued on: 01/10/1984
Inventor: Adam

Electrically alterable, nonvolatile floating gate memory device
Patent #: 4513397
Issued on: 04/23/1985
Inventor: Ipri ,   et al.

Electrically alterable, nonvolatile floating gate memory device Patent #: 4618876
Issued on: 10/21/1986
Inventor: Stewart ,   et al.

Inventor

Application

No. 451066 filed on 12/15/1989

US Classes:

438/266, Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)438/261, Multiple interelectrode dielectrics or nonsilicon compound gate insulator438/594Tunnelling dielectric layer

Examiners

Primary: Hearn, Brian E.
Assistant: Thomas, Tom

Attorney, Agent or Firm

Foreign Patent References

  • 0091561 JP 06/13/1982
  • 0209165 JP 12/13/1983
  • 0045863 JP 02/13/1988
  • 0142869 JP 06/13/1988
  • 0043862 JP 03/13/1990

International Class

H01L 021/336

Foreign Application Priority Data

1987-12-02 JP

Abstract

An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

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