NMOS transistor having inversion layer source/drain contacts

Patent 5047361 Issued on September 10, 1991. Estimated Expiration Date:

July 6, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3442721

3657614

Semiconductor devices having surface state control
Patent #: 3983574
Issued on: 09/28/1976
Inventor: Statz , et al.

Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states Patent #: 4047974
Issued on: 09/13/1977
Inventor: Harari

Inventors

Assignee

Texas Instruments Incorporated

Application

No. 549507 filed on 07/06/1990

US Classes:

438/288, Having step of storing electrical charge in gate dielectric257/405, With gate insulator containing specified permanent charge257/900, MOSFET TYPE GATE SIDEWALL INSULATING SPACER257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.162, Insulating materials for IGFET (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/595Having sidewall structure

Examiners

Primary: Hearn, Brian E.
Assistant: Picardat, Kevin M.

Attorney, Agent or Firm

Sharp; Melvin, Comfort; James T., Merrett; N. Rhys

International Class

H01L 021/265

Abstract

A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).