Bizarre Patents
An enclosure for small animals which is wearable on the front or back of an animate being.
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
US Patent 5047361 - NMOS transistor having inversion layer source/drain contacts
US Patent Issued on September 10, 1991
Estimated Patent Expiration Date:
July 6, 2010Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
July 6, 2010Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b). | InventorsAssigneeApplicationNo. 549507 filed on 07/06/1990US Classes:438/288, Having step of storing electrical charge in gate dielectric257/405, With gate insulator containing specified permanent charge257/900, MOSFET TYPE GATE SIDEWALL INSULATING SPACER257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.162, Insulating materials for IGFET (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/595Having sidewall structureExaminersPrimary: Hearn, Brian E.Assistant: Picardat, Kevin M. Attorney, Agent or FirmUS Patent References3442721, 3657614, 3983574, Semiconductor devices having surface state controlIssued on: 09/28/1976 Inventor: Statz , et al.4047974Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states Issued on: 09/13/1977 Inventor: Harari International ClassH01L 021/265 |
