U.S. patents available from 1976 to present.
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Process for forming a feature on a substrate without recessing the surface of the substrate

Patent 5034351 Issued on July 23, 1991. Estimated Expiration Date: Icon_subject October 1, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Process for forming semiconductor devices using electron-sensitive resist patterns with controlled line profiles
Patent #: 4283483
Issued on: 08/11/1981
Inventor: Coane

Process for making a T-gated transistor
Patent #: 4700462
Issued on: 10/20/1987
Inventor: Beaubien ,   et al.

Technique for forming planarized gate structure
Patent #: 4818725
Issued on: 04/04/1989
Inventor: Lichtel, Jr. ,   et al.

4927776

Process for fabricating small size electrodes in an integrated circuit
Patent #: 4968646
Issued on: 11/06/1990
Inventor: Blanchard, et al.

Method of making a self-aligned field-effect transistor by the use of a dummy-gate
Patent #: 4975382
Issued on: 12/04/1990
Inventor: Takasugi

Process for forming a self-aligned FET having a T-shaped gate structure Patent #: 4997778
Issued on: 03/05/1991
Inventor: Sim, et al.

Inventors

Assignee

Application

No. 590856 filed on 10/01/1990

US Classes:

438/202, Including bipolar transistor (i.e., BiCMOS)257/E21.033, Comprising inorganic layer (EPO)257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.206, Lithography, isolation, or planarization-related aspects of making conductor-insulator-semiconductor structure, e.g., sub-lithography lengths; to solve problems arising at crossing with side of device isolation (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E21.696, Bipolar and MOS technologies (EPO)438/669, And patterning of conductive layer438/703Plural coating steps

Examiners

Primary: Hearn, Brian E.
Assistant: Picardat, Kevin M.

Attorney, Agent or Firm

Foreign Patent References

  • 58-056472 JP 04/13/1983

International Class

H01L 021/465

Abstract

A process for forming a feature on a substrate without etching into the surface of the substrate and causing recessed regions. A first layer of material is deposited to overlie the substrate and is formed of a different material to the substrate. The first layer is patterned, using conventional photolithography, to form windows in the first layer of material which expose a substrate surface. The etch selectively etches the first layer of material without substantially etching into the substrate material. A second layer of material, which is the same material as the substrate, is deposited to overlie the first layer of material and makes physical contact with the substrate through the windows patterned in the first layer. The second layer is blanket etched so that isolated regions are formed in regions defined by the windows patterned in the first layer.

Other References

  • S. Wolf and R. W. Tauber, Silicon Processing for the VLSI Era, Sunset Beach, Calif. 1986, vol. 1-Process Technology, pp. 155-15
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