Method of forming an electrical via structure
April 27, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for controlling the wall inclination of a plasma etched via hole Composition and thickness variation in dielectric layers Process for etching tapered vias in silicon dioxide Etching method Method for forming an electrical contact in an integrated circuit Double layer photoresist technique for side-wall profile control in plasma etching processes (RIE) Plasma process for making metal-semiconductor ohmic type contacts Process of making via holes in a double-layer insulation Patent #: 4816115 InventorsApplicationNo. 515813 filed on 04/27/1990US Classes:216/18, Filling or coating of groove or through hole with a conductor to form an electrical interconnection216/48, Mask is exposed to nonimaging radiation216/66, Using ion beam, ultraviolet, or visible light257/E21.578, Tapered via holes (EPO)257/E23.145, Via connections in multilevel interconnection structure (EPO)430/313, With formation of resist image, and etching of substrate or material deposition430/317, Insulative or nonmetallic dielectric etched430/318Metal etchedExaminersPrimary: Powell, William A.Attorney, Agent or FirmInternational ClassesB44C 001/22B29C 037/00 C23F 001/02 C03C 015/00 AbstractA via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45° to the lower metal layer (6), and preferably about 30°-45°, to enable a generally uniform width for the upper metallization (28) in the via (26). A non-erodible mask (10) is established over the dielectric layer (8) lateral to the via (26) during fabrication to prevent the propagation of pinhole defects from the erodible mask (18) into the dielectric (8), and is normally removed prior to completing the structure.Other References
Field of SearchFeedthroughHollow (e.g., plated cylindrical hole) Including multiple resist image formation With formation of resist image, and etching of substrate or material deposition Etching of substrate and material deposition Multiple etching of substrate Insulative or nonmetallic dielectric etched Metal etched By forming conductive walled aperture in base Sputter etching Etching specified material Organic |
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