Patent ReferencesProcess for direct thermal nitridation of silicon semiconductor devices Method for forming a nitride insulating film on a silicon semiconductor substrate surface by direct nitridation Native oxide reduction for sealing nitride deposition Method for wafer treating Annealing process to stabilize PECVD silicon nitride for application as the gate dielectric in MOS devices Patent #: 4962065 InventorsApplicationNo. 605748 filed on 10/30/1990US Classes:438/762, At least one layer formed by reaction with substrate257/E21.226, Dry cleaning (EPO)257/E21.293, Of silicon nitride (EPO)257/E21.396, Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO)438/396, Stacked capacitor438/775, Nitridation438/791, Silicon nitride formation438/906, CLEANING OF WAFER AS INTERIM STEP438/974SUBSTRATE SURFACE PREPARATIONExaminersPrimary: Hearn, Brian E.Assistant: Dang, Trung Attorney, Agent or FirmInternational ClassH01L 000/00AbstractA process for forming silicon nitride layers on silicon substrates which includes initially heating the silicon substrates in a rapid thermal processor and in a substantially oxygen-free and residual moisture free environment to form a thin Si3 N4 layer directly on the silicon surface which is free of any measurable native SiO2 thereon. Then, the nitridized wafers are transferred into a conventional nitride furnace where the thin Si3 N4 layers may be increased in thickness by a desired amount. Typically, the initial or first Si3 N4 layer thickness will be about 10-30 angstroms and the second Si3 N4 layer will be on the order of 80 angstroms or more to form a composite Si3 N4 layer of about 100-150 angstroms in total thickness. This novel process and the high dielectric constant integrated circuit capacitors produced thereby are highly useful in the manufacture of certain very large scale integrated circuit (VLSI) components such as dynamic random access memories and the like. | |