Organization of an integrated cache unit for flexible usage in cache system design
June 18, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBuffer store including control apparatus which facilitates the concurrent processing of a plurality of commands Multiplexed directory for dedicated cache memory system Cache memory architecture with decoding Multilevel cache system with graceful degradation capability Cache/disk file status indicator with data protection feature Cache locking controls in a multiprocessor Quasi content addressable memory Cache coherence mechanism based on locking Cache memory control apparatus Stack frame cache on a microprocessor chip InventorAssigneeApplicationNo. 146009 filed on 01/20/1988US Classes:711/128, Associative711/118, Caching711/134, Combined replacement modes711/136, Least recently used711/145Access control bitExaminersPrimary: Shaw, Gareth D.Assistant: Kriess, Kevin A. Attorney, Agent or FirmInternational ClassG06F 012/08AbstractMethods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be performed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency. | |
