Patent ReferencesBacking store access coordination in a multi-processor system Diagnostic apparatus in a data processing system Continuous updating of cache store Command queue apparatus included within a cache unit for facilitating command sequencing Multilevel storage system having unitary control of data transfers Duplicate tag store for cached multiprocessor system Cache memory command buffer circuit Hierarchical memory system having cache/disk subsystem with command queues for plural disks Three level memory hierarchy using write and share flags Multiprocessing system including a shared cache InventorApplicationNo. 159016 filed on 02/22/1988US Classes:711/122, Hierarchical caches711/118CachingExaminersPrimary: Shaw, Gareth D.Assistant: Kulik, Paul V. Attorney, Agent or FirmInternational ClassG06F 013/00AbstractA multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache. A second level store queue, associated with each processor, receives the data and/or instructions from its first level store queue and temporarily stores the information therein. For sequential stores, the data and/or instructions are stored in corresponding second level write buffers. For non-sequential stores, the data and/or instructions bypass the corresponding second level write buffers and are stored directly in a final L2 cache write buffer. When stored in the second level writer buffers, access to the shared second level cache is requested. | |