U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage

Patent 5023776 Issued on June 11, 1991. Estimated Expiration Date: Icon_subject June 11, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Multiprocessing system including a shared cache
Patent #: 4445174
Issued on: 04/24/1984
Inventor: Fletcher

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Inventor

Application

No. 159016 filed on 02/22/1988

US Classes:

711/122, Hierarchical caches711/118Caching

Examiners

Primary: Shaw, Gareth D.
Assistant: Kulik, Paul V.

Attorney, Agent or Firm

International Class

G06F 013/00

Abstract

A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache. A second level store queue, associated with each processor, receives the data and/or instructions from its first level store queue and temporarily stores the information therein. For sequential stores, the data and/or instructions are stored in corresponding second level write buffers. For non-sequential stores, the data and/or instructions bypass the corresponding second level write buffers and are stored directly in a final L2 cache write buffer. When stored in the second level writer buffers, access to the shared second level cache is requested.

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