CMOS processes
August 3, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for minimum overlap silicon gate devices Shadow masking process for forming source and drain regions for field-effect transistors and like regions Very high density cells comprising a ROM and method of manufacturing same Method for the simultaneous manufacture of fast short channel and voltage-stable MOS transistors in VLSI circuits Method of making tri-well CMOS by self-aligned process Method of producing a large-scale integrated MOS field-effect transistor circuit Method of making a gated isolated structure Patent #: 4849366 InventorsApplicationNo. 562263 filed on 08/03/1990US Classes:438/200, And additional electrical device257/369, Complementary insulated gate field effect transistors257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.633, With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)438/227, Having well structure of opposite conductivity type438/231Plural doping stepsExaminersPrimary: Chaudhuri, OlikAssistant: Wilczewski, M. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 021/336 AbstractIn one aspect of the invention, a semiconductor chip having an array of memory cells and peripheral integrated circuitry comprises:CMOS transistors in the memory array, with the n-channel transistors of the array being formed without LDD regions; andthe peripheral integrated circuitry comprising n-channel FET transistors, with such n-channel FET transistors being formed with LDD regions. In another aspect, disclosed is a CMOS process which produces a combination of n-channel MOS transistors having LDD spacers, n-channel MOS transistors void of LDD spacers, and p-channel MOS transistors. | |
