Method of etching for integrated circuits with planarized dielectric
Patent 5022958 Issued on June 11, 1991. Estimated Expiration Date: 
June 27, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 27, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultilayer planarizing structure for lift-off technique Process of making via holes in a double-layer insulation Semiconductor devices having multi-level metal interconnects Planarizing contact etch Via-filling and planarization technique Method for planarization of a semiconductor device prior to metallization Patent #: 4966865 InventorsAssigneeApplicationNo. 544705 filed on 06/27/1990US Classes:438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/E21.252, By dry-etching (EPO)257/E21.577, By forming via holes (EPO)438/586, Combined with formation of ohmic contact to semiconductor region438/699, Plural coating steps438/702Plural coating stepsExaminersPrimary: Powell, William A.Attorney, Agent or FirmInternational ClassesB44C 001/22C03C 015/00 C03C 025/06 AbstractAn integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric. | |
