Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
January 30, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3614745 System and method for concurrent and pipeline processing employing a data driven network Data processing apparatus for highly parallel execution of stored programs Single chip MOS computer with expandable memory Modular system controller for a transition machine Data flow component for processor and microprocessor systems Reduction processor for executing programs stored as treelike graphs employing variable-free applicative language codes Concurrent processing elements for using dependency free code Syntactically self-structuring cellular computer Dynamic activity-creating data-driven computer architecture InventorsApplicationNo. 474707 filed on 01/30/1990US Classes:712/25Data driven or demand driven processorExaminersPrimary: Lee, Thomas C.Attorney, Agent or FirmInternational ClassG06F 015/82AbstractA data-flow architecture and software environment for high-performance signal and data procesing. The programming environment allows applications coding in a functional high-level language 20 which a compiler 30 converts to a data-flow graph form 40 which a global allocator 50 then automatically partitions and distributes to multiple processing elements 80, or in the case of smaller problems, coding in a data-flow graph assembly language so that an assembler 15 operates directly on an input data-flow graph file 13 and produces an output which is then sent to a local allocator 17 for partitioning and distribution. In the former case a data-flow processor description file 45 is read into the global allocator 50, and in the latter case a data-flow processor description file 14 is read into the assembler 15. The data-flow processor 70 consists of multiple processing elements 80 connected in a three-dimensional bussed packet routing network. Data enters and leaves the processor 70 via input/output devices 90 connected to the processor. The processing elements are designed for implementation in VLSI (Very large scale integration) to provide realtime processing with very large throughput. The modular nature of the computer allows adding more processing elements to meet a range of throughout and reliability requirements. Simulation results have demonstrated high-performance operation, with over 64 million operations per second being attainable using only 64 processing elements.Other References
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