Method of forming conductive channel extensions to active device regions in CMOS device
Method of manufacturing CMOS devices
Process of making twin well VLSI CMOS
Process for fabricating semiconductor integrated circuit device
Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation Patent #: 4745086
ApplicationNo. 485029 filed on 02/26/1990
US Classes:438/231, Plural doping steps257/369, Complementary insulated gate field effect transistors257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.636, Silicided or salicided gate conductors (EPO)438/227Having well structure of opposite conductivity type
ExaminersPrimary: Chaudhuri, Olik
Assistant: Wilczewski, M.
Attorney, Agent or Firm
Foreign Patent References
International ClassesH01L 021/265
AbstractAn improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.