High power MOSFET with low on-resistance and high breakdown voltage
Highly integrated semiconductor memory device
Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide Patent #: 4593302
ApplicationNo. 331449 filed on 03/31/1989
US Classes:257/339, With means to increase breakdown voltage257/341, Plural sections connected in parallel (e.g., power MOSFET)257/E29.027, Surface layout of MOS gated device (e.g., DMOSFET or IGBT) (EPO)257/E29.109, Characterized by concentration or distribution of impurities in bulk material (EPO)257/E29.257Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)
ExaminersPrimary: James, Andrew J.
Assistant: Ngo, Ngan Van
Attorney, Agent or Firm
Foreign Patent References
International ClassesH01L 029/10
Foreign Application Priority Data1988-04-01 JP
AbstractIn a vertical field effect transistor including a source electrode and a gate on the front surface of a semiconductor substrate having one conductivity type and a drain electrode on the back surface of the substrate, the semiconductor device of the present invention has the structure wherein a connection region of one conductivity type positioned between two channel forming base regions of the opposite conductivity type is formed by a semiconductor layer having a higher impurity concentration than the drain region of the one conductivity type, and the surface portion of the connection region which is connected to the channel has a lower impurity concentration than the connection region.