U.S. patents available from 1976 to present.
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Configurable set associative cache with decoded data element enable lines

Patent 5014195 Issued on May 7, 1991. Estimated Expiration Date: Icon_subject May 10, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Virtual cache
Patent #: 4264953
Issued on: 04/28/1981
Inventor: Douglas ,   et al.

Cache organization enabling concurrent line castout and line fetch transfers with main storage
Patent #: 4317168
Issued on: 02/23/1982
Inventor: Messina ,   et al.

Cache synonym detection and handling mechanism
Patent #: 4332010
Issued on: 05/25/1982
Inventor: Messina ,   et al.

Second level cache replacement method and apparatus
Patent #: 4464712
Issued on: 08/07/1984
Inventor: Fletcher

Cache sharing control in a multiprocessor
Patent #: 4484267
Issued on: 11/20/1984
Inventor: Fletcher

Set associative sector cache
Patent #: 4493026
Issued on: 01/08/1985
Inventor: Olnowich

Method of performing a call operation in a digital data processing system having microcode call and return operations
Patent #: 4493027
Issued on: 01/08/1985
Inventor: Katz ,   et al.

Hierarchical memory system including separate cache memories for storing data and instructions
Patent #: 4719568
Issued on: 01/12/1988
Inventor: Carrubba ,   et al.

Odd/even storage in cache memory
Patent #: 4724518
Issued on: 02/09/1988
Inventor: Steps

Interleaved set-associative memory Patent #: 4736293
Issued on: 04/05/1988
Inventor: Patrick

Inventors

Assignee

Application

No. 522503 filed on 05/10/1990

US Classes:

711/128, Associative365/49, ASSOCIATIVE MEMORIES365/230.01, ADDRESSING711/171Based on data size

Examiners

Primary: Fears, Terrell W.

Attorney, Agent or Firm

International Class

G11C 013/00

Abstract

A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.

Other References

  • The IBM Technical Disclosure Bulletin, vol. 27, No. 10B, Mar. 1985, pp. 6084-6088
  • Smith, A. J., "Cache Memories", in Computing Surveys, vol. 14, No. 3, Sep. 1982
  • Strecker, W. D., "Cache Memories for PDP-11 Family Computers", in Computer Engineering, by Bell, Mudge, and McNamara, pp. 263-267, (1978: Digital Equipment Corporation, Bedford, Mass.
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