Cache organization enabling concurrent line castout and line fetch transfers with main storage
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Cache sharing control in a multiprocessor
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Interleaved set-associative memory Patent #: 4736293
ApplicationNo. 522503 filed on 05/10/1990
US Classes:711/128, Associative365/49, ASSOCIATIVE MEMORIES365/230.01, ADDRESSING711/171Based on data size
ExaminersPrimary: Fears, Terrell W.
Attorney, Agent or Firm
International ClassG11C 013/00
AbstractA set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.