Semiconductor memory device

Patent 5010518 Issued on April 23, 1991. Estimated Expiration Date:

October 16, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Self restoring ferroelectric memory Patent #: 4873664
Issued on: 10/10/1989
Inventor: Eaton, Jr.

Inventor

Toda, Haruki

Application

No. 422051 filed on 10/16/1989

US Classes:

365/145, Ferroelectric257/E27.104, Ferroelectric non-volatile memory structure (EPO)365/149, Capacitors365/210Reference or dummy element

Examiners

Primary: Popek, Joseph A.

Attorney, Agent or Firm

Finnegan, Henderson, Farabow, Garrett and Dunner

International Class

G11C 011/34

Foreign Application Priority Data

1988-10-19 JP

Abstract

A semiconductor memory device comprises a first bit line, a second bit line paired with the first bit line, a third bit line branch-connected with the first bit line, a fourth bit line paired with the third bit line and branch-connected with the second bit line, a memory cell array connected to the bit lines, a first reference cell, and a second reference cell. The first reference cell is connected to the first bit line and the third bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from memory cells in the memory cell array. And the second reference cell is connected to the second bit line and the fourth bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from the memory cells in the memory cell array. The memory cell array is a non-volatile type constituted by ferroelectric cells.

Other References

"A New Memory Technology Is About to Hit The Market", Electronics, pp. 91-95, Feb. 18, 1988
Evans, et al., "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1171-1175, Oct. 198