U.S. patents available from 1976 to present.
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Method and apparatus for checksum address generation in a fail-safe modular memory

Patent 5007053 Issued on April 9, 1991. Estimated Expiration Date: Icon_subject November 30, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Memory checking method
Patent #: 4368532
Issued on: 01/11/1983
Inventor: Imazeki ,   et al.

Method for detecting intermittent error in volatile memory
Patent #: 4698808
Issued on: 10/06/1987
Inventor: Ishii

Fail safe architecture for a computer system
Patent #: 4726024
Issued on: 02/16/1988
Inventor: Guziak ,   et al.

Memory integrity checking system for a gaming device
Patent #: 4727544
Issued on: 02/23/1988
Inventor: Brunner ,   et al.

Self-testing memory
Patent #: 4782486
Issued on: 11/01/1988
Inventor: Lipcon ,   et al.

Data terminal with capability of checking memory storage capacity as well as program execution parameters Patent #: 4807186
Issued on: 02/21/1989
Inventor: Ohnishi ,   et al.

Inventors

Application

No. 278104 filed on 11/30/1988

US Classes:

714/718, Memory testing714/6, Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)714/722Performing arithmetic function on memory contents

Examiners

Primary: Fleming, Michael R.

Attorney, Agent or Firm

International Class

G06F 011/10

Abstract

A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.

Other References

  • David A. Patterson, Garth Gibson, Randy H. Katz, "A Case For Redundant Arrays of Inexpensive Disks (RAID)", published in ACM SIGMOD Conference, Chicago, Ill., (May 1988
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