Microprogrammed programmable controller
Data transmission/reception installation with parallel/serial and serial/parallel character conversion for data exchange between communicating data processing systems
Bus connection system
Data processing system having unique bus control operation
Adapter for interfacing between two buses
Modular programmable controller
Mailing system peripheral interface with communications formatting memory
I/O Adapter with direct memory access to I/O control information
Data processing system with processors having different processing speeds sharing a common bus
Addressable buffer circuit with address incrementer independently clocked by host computer and external storage device controller
ApplicationNo. 213401 filed on 06/30/1988
US Classes:710/57Fullness indication
ExaminersPrimary: Eng, David Y.
Assistant: Pappas, George C.
Attorney, Agent or Firm
International ClassesG06F 003/00
AbstractAn information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.