Raised source/drain transistor
December 22, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of fabricating a monolithic integrated circuit structure Method of making integrated circuits using metal silicide contacts Silicon gigabit metal-oxide-semiconductor device processing Integrated circuit structure having intermediate metal silicide layer and method of making same Method of producing semiconductor device Submicron FET structure and method of making Gate electrode sidewall isolation spacer for field effect transistors Method for the self-aligned silicide formation in IC fabrication Method for etching contact vias in a semiconductor device Patent #: 4753709 InventorsAssigneeApplicationNo. 289346 filed on 12/22/1988US Classes:257/288, Having insulated electrode (e.g., MOSFET, MOS diode)257/900, MOSFET TYPE GATE SIDEWALL INSULATING SPACER257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E29.04Of field-effect transistors with insulated gate (EPO)ExaminersPrimary: Hille, RolfAssistant: Tran, Minh Loan Attorney, Agent or FirmForeign Patent References
International ClassH01L 029/78AbstractA raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).Other References
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