Semiconductor device having an improved wiring pattern
Patent 4994894 Issued on February 19, 1991. Estimated Expiration Date: 
January 5, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 5, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor device providing a contact structure which can be miniaturized Patent #: 4549199 InventorApplicationNo. 293848 filed on 01/05/1989US Classes:257/774, Via (interconnection hole) shape257/E23.019Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)ExaminersPrimary: Hille, RolfAssistant: Fahmy, Wael Attorney, Agent or FirmInternational ClassH01L 023/48Foreign Application Priority Data1988-01-21 JPAbstractA semiconductor device comprises a semiconductor substrate having a diffused region and an element region, and the diffused region and the element region overlap at least partially. An insulating layer having a contact hole is provided at the surface of the substrate. A wiring layer crosses over the contact hole to form at least four crossing points with respect to the contact hole. The crossing points over the element region correspond to the overlap between the diffused region and the element region. | |
