Radiation hardened field oxides for NMOS and CMOS-bulk and process for forming
September 20, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3751722 Monolithic integration of logic, control and high voltage interface circuitry Isolation for high density integrated circuits Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition Method of making a trench isolated device Method for forming a void free isolation structure utilizing etch and refill techniques Trench etch process for dielectric isolation Process for producing zones for the electrical isolation of the components of an integrated circuit Methods for forming shapes or blocks of no mix cements Patent #: 4839115 InventorsAssigneeApplicationNo. 247053 filed on 09/20/1988US Classes:438/227, Having well structure of opposite conductivity type257/E21.557, Introducing electrical active impurities in local oxidation region solely for forming channel stoppers (EPO)438/298, Doping region beneath recessed oxide (e.g., to form chanstop, etc.)438/443, Etchback of recessed oxide438/450, Implanting through recessed oxide438/953, MAKING RADIATION RESISTANT DEVICE438/981UTILIZING VARYING DIELECTRIC THICKNESSExaminersPrimary: Hearn, Brian E.Assistant: McAndrews, Kevin Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/265AbstractThe field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET. | |
