Optimal test generation for finite state machine models
Patent 4991176 Issued on February 5, 1991. Estimated Expiration Date: 
June 7, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 7, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for generating verification tests Method of generating test patterns for logic network devices Viterbi decoder with reduced number of data move operations Patent #: 4748626 InventorsAssigneeApplicationNo. 362724 filed on 06/07/1989US Classes:714/738, Including test pattern generator714/33Derived from analysis (e.g., of a specification or by stimulation)ExaminersPrimary: Smith, JerryAssistant: Beausoliel, Robert Attorney, Agent or FirmInternational ClassG06F 011/00AbstractFaster, yet, completely efficient and exhaustive testing is afforded an entity (e.g., protocol, VLSI circuit, software application) represented as finite state machines by employing the present method in which test sequences are generated according to minimum cost function rules. Minimum cost unique signatures are developed for state identification of the finite state machine. Based upon the minimum cost unique signatures, a minimum cost test sequence is generated to cover every state transition of the finite state machine. As a result, every testable aspect of the entity is guaranteed to be tested using a minimum number of steps which represents a considerable cost savings.Other References
Field of SearchPLURAL, AUTOMATICALLY SEQUENTIAL TESTS | |
