Personal computer bus interface chip with multi-function address relocation pins
April 13, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInterface adaptor architecture Adapter for interfacing between two buses System bus for an emulated multichannel system Bus interface unit Microprocessor capable of automatically performing multiple bus cycles Bus master capable of relinquishing bus on request and retrying bus cycle IC input circuitry programmable for realizing multiple functions from a single input Logically transportable microprocessor interface control unit permitting bus transfers with different but compatible other microprocessors Patent #: 4727477 InventorsAssigneeApplicationNo. 181138 filed on 04/13/1988US Classes:326/82, Current driving (e.g., fan in/out, off chip driving, etc.)712/38Offchip interfaceExaminersPrimary: Eng, David Y.International ClassesG06F 013/12G06F 013/14 G06F 013/42 AbstractAn integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip. The present interface integrated chip combines (a) command decode circuitry for receiving coded signals from the MCA bus and for generating decoded command signals for peripheral devices, (b) pin control circuitry which controls multi-function pins, (c) bus arbitration control circuitry, (d) POS Programmable Option Select register control circuitry to facilitate adapter identification support, (e) ready logic circuitry to facilitate synchronous ready signal generation, (f) circuitry to facilitate device error reporting, (g) external data buffer control, (h) bus response signal generation circuitry, and (j) circuitry to support memory and I-O relocation. The above combination of functions is provided on a single integrated circuit thereby efficiently utilizing the limited number of I-O pins available on the integrated circuit.Other References
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