Technique for parallel synchronization
July 26, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultidimensional parallel access computer memory system Scientific processor Arrays of machines such as computers Synchronous and conditional inter-program control apparatus for a computer system Logic simulation machine Double redundant processor Array processor architecture connection network Accelerator processor for a data processing system Array processor architecture Extra stage cube InventorApplicationNo. 224846 filed on 07/26/1988US Classes:712/203, Multiprocessor instruction711/150Simultaneous access regulationExaminersPrimary: Eng, David Y.Attorney, Agent or FirmForeign Patent References
International ClassG06F 013/00AbstractA parallel synchronization technique utilizing a combining network in which two processors synchronize by having one processor suspend operation while the other processor becomes the agent for the one processor, while continuing to operate on its own behalf. This reduces the access requests and subsequent contention caused by multiple concurrent requests to a common variable.Other References
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