Dynamic random access memory cell
Patent 4989055 Issued on January 29, 1991. Estimated Expiration Date: 
June 15, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 15, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVertical DRAM cell and method Two square memory cells Patent #: 4769786 InventorAssigneeApplicationNo. 366561 filed on 06/15/1989US Classes:257/302, Vertical transistor257/411, Composite or layered gate insulator (e.g., mixture such as silicon oxynitride)257/E27.084, Dynamic random access memory, DRAM, structure (EPO)257/E29.262Vertical transistor (EPO)ExaminersPrimary: Jackson, JeromeAssistant: Meier, Stephen D. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/78H01L 027/02 AbstractThe described embodiments of the present invention provide a dynamic random access memory cell and array. The memory cell provides a three transistor storage device where the storage signal is stored on the gate of a storage transistor. All three transistors are integrated into a trench thereby providing the density equal to that of the densest of modern day DRAM cells. By using the three transistor concept, the first embodiment of the present invention provides a gain for the stored charge. Because the storage transistor amplifies the stored charge, the reduced capacitance of ultra-dense DRAM cells is overcome and adequate data sensing may be accomplished using capacitances much smaller than those useful in the single transistor, single capacitor DRAM cell.Other References
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