Self-zeroing analog-to-digital conversion system
Parallel analog-to-digital converter with increased resolution
Analogue to digital converters Patent #: 4288873
ApplicationNo. 244552 filed on 09/12/1988
US Classes:341/166, Intermediate conversion to time interval341/118CONVERTER COMPENSATION
ExaminersPrimary: Shoop, William M. Jr.
Assistant: Hoff, Marc S.
Attorney, Agent or Firm
Foreign Patent References
International ClassH03M 001/50
Foreign Application Priority Data1985-12-28 JP
AbstractAn analog/digital converter includes a peak holding circuit for holding a peak voltage of input analog data and a peak time detecting circuit for detecting a point of time when the input analog data reaches a peak voltage. Also included is a constant current discharging circuit for discharging the peak voltage held in the peak holding circuit at a constant current from the peak point of time detected by the peak time detecting circuit. The converter also includes a zero time detecting circuit for detecting a zero point of time when a voltage held in the peak holding circuit is reduced to zero and a time to digital converting circuit for counting a number of pulses in a pulse line obtained by gating clock pulses during a period of time from the peak time detected by the peak detecting circuit to the zero time detected by the zero time detecting circuit, the time to digital converting including a counter to output digital data corresponding to the input analog data. A positive offset analog voltage is added to the input analog data and a digital compensator compensates the digital data obtained by the time to digital converting circuit by providing a negative offset digital value approximately corresponding to the positive offset analog voltage, more correctly, equal to a number of pulses in a pulse line passing through a clock gate of the time-to-digital converting circuit for a period of time during which the input analog data has a value equal to zero.