Serial data transfer system
Patent 4984190 Issued on January 8, 1991. Estimated Expiration Date: 
August 20, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 20, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTwo-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations Patent #: 4689740 InventorsAssigneeApplicationNo. 569539 filed on 08/20/1990US Classes:709/237, Computer-to-computer handshaking713/400SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSESExaminersPrimary: Shaw, Dale M.Assistant: Jaffe, Michael A. Attorney, Agent or FirmInternational ClassG06F 013/00Foreign Application Priority Data1986-09-01 JPAbstractHerein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal. When the reception of the serial data on the data line is ended, the output circuit outputs the reception confirmation signal to the data line in synchronism with the first or second signal. | |
