Method of making a CMOS device with trench isolation device
Patent 4980306 Issued on December 25, 1990. Estimated Expiration Date: 
November 1, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 1, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for fabricating CMOS devices with guardband High-voltage CMOS process CMOS Process with unique plasma etching step Semiconductor device having isolation regions Method of manufacturing semiconductor device with MIS capacitor Patent #: 4645564 InventorAssigneeApplicationNo. 265698 filed on 11/01/1988US Classes:438/222, With epitaxial semiconductor layer formation257/E21.546, Using trench refilling with dielectric materials (EPO)257/E21.551, Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (EPO)257/E21.642, Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO)438/429And epitaxial semiconductor formation in grooveExaminersPrimary: Hearn, Brian E.Assistant: Thomas, T. Attorney, Agent or FirmInternational ClassH01L 021/76Foreign Application Priority Data1987-11-11 JPAbstractA semiconductor device of the complementary metal-insulator semiconductor type is composed of a pair of N-type metal oxide semiconductor transistor formed on a P-type silicon substrate and P-type metal oxide semiconductor transistor formed on an n-type well disposed within the p-type substrate. An isolation tranch is disposed between the pair of adjacent transistors, and has one sidewall bordering the well, another opposed sidewall bordering the substrate, and a bottom wall. A selective epitaxial film of p-type is selectively epitaxially deposited on the sidewalls and bottom wall of the trench. The epitaxial film has a dopant density greater than that of the substrate. An insulation oxide material is filled within the trench so as to effectively isolate the pair of transistors from each other. | |
