U.S. patents available from 1976 to present.
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LDD transistor process having doping sensitive endpoint etching

Patent 4978626 Issued on December 18, 1990. Estimated Expiration Date: Icon_subject September 2, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Inventor: Gardiner ,   et al.

Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
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End point detection method for physical etching process
Patent #: 4358338
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Monitoring technique for plasma etching
Patent #: 4602981
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Trench etch endpoint detection by LIF
Patent #: 4675072
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Method for fabricating MOS transistors having gates with different work functions
Patent #: 4714519
Issued on: 12/22/1987
Inventor: Pfiester

Method of detecting the endpoint of the etch of epitaxially grown silicon
Patent #: 4717446
Issued on: 01/05/1988
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Source drain doping technique
Patent #: 4757026
Issued on: 07/12/1988
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Method of fabricating a LDDFET with self-aligned silicide
Patent #: 4818715
Issued on: 04/04/1989
Inventor: Chao

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Inventors

Assignee

Application

No. 240013 filed on 09/02/1988

US Classes:

438/220, Isolation by PN junction only216/67, Using plasma216/79, Etching silicon containing substrate257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.205, Characterized by sectional shape, e.g., T-shape, inverted T, spacer (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.635, With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)257/E29.255, With field effect produced by insulated gate (EPO)257/E29.269, With overlap between lightly doped extension and gate electrode (EPO)438/231, Plural doping steps438/305Plural doping steps

Examiners

Primary: Chaudhuri, Olik
Assistant: Wilczewski, M.

Attorney, Agent or Firm

Foreign Patent References

  • 0085916 EP 08/13/1983
  • 3813665 DE 11/13/1988
  • 0070762 JP 06/13/1979
  • 0083267 JP 06/13/1980
  • 0126957 JP 10/13/1981
  • 0045184 JP 10/13/1983
  • 0110169 JP 06/13/1984
  • 0034068 JP 02/13/1985
  • 0055665 JP 03/13/1985
  • 0007564 JP 01/13/1989
  • 0133365 JP 05/13/1989
  • 0133366 JP 05/13/1989

International Classes

H01L 021/265
H01L 021/28
H01L 027/092

Abstract

An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

Other References

  • Huang et al., "A Novel Submicron LLD Transistor with Inverse-T Gate Structure", IEDM, 12/1986, pp. 742-745
  • "Simultaneous Formation of Shallow-Deep Stepped Source/Drain For Sub-Micron CMOS", by C. S. Oh et al., 1988, Symposium on VLSI Technology/Digest of Techical Papers, pp. 73-74, May 10-13, 1988
  • "A Novel Submicron LDD Transistor With Inverse-T Gate Structure", by Tiao-Yuan Huang et al., 1986 IEEE International Electron Devices Meeting Technical Digest, pp. 742-745, Dec. 7-10, 1986
  • "The Impact of Gate-Drain Overlapped LDD (Gold) For Deep Submicron VLSI's", by Tyuichi Izawa et al., 1987 IEEE International Electron Device Meeting Technical Digest, pp. 38-41, Dec. 6-9, 198
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