Patent ReferencesMethod of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon End point detection method for physical etching process Plasma-assisted etch process with endpoint detection Monitoring technique for plasma etching Trench etch endpoint detection by LIF Method for fabricating MOS transistors having gates with different work functions Method of detecting the endpoint of the etch of epitaxially grown silicon Source drain doping technique Method of fabricating a LDDFET with self-aligned silicide InventorsAssigneeApplicationNo. 240013 filed on 09/02/1988US Classes:438/220, Isolation by PN junction only216/67, Using plasma216/79, Etching silicon containing substrate257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.205, Characterized by sectional shape, e.g., T-shape, inverted T, spacer (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.635, With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)257/E29.255, With field effect produced by insulated gate (EPO)257/E29.269, With overlap between lightly doped extension and gate electrode (EPO)438/231, Plural doping steps438/305Plural doping stepsExaminersPrimary: Chaudhuri, OlikAssistant: Wilczewski, M. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 021/28 H01L 027/092 AbstractAn LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.Other References
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