Trench dual-gate MOSFET

Patent 4975754 Issued on December 4, 1990. Estimated Expiration Date:

June 29, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Process for manufacturing a Schottky FET device using metal sidewalls as gates Patent #: 4729966
Issued on: 03/08/1988
Inventor: Koshino , et al.

Inventors

Application

No. 373059 filed on 06/29/1989

US Classes:

257/329, Gate controls vertical charge flow portion of channel (e.g., VMOS device)257/365, With plural, separately connected, gate electrodes in same device257/E29.262, Vertical transistor (EPO)257/E29.264With multiple gate structure (EPO)

Examiners

Primary: Hille, Rolf
Assistant: Fahmy, Wael

Attorney, Agent or Firm

Finnegan, Henderson, Farabow, Garrett, and Dunner

Foreign Patent References

58-125873 JP 07/22/1983

International Classes

H01L 029/10
H01L 029/06

Foreign Application Priority Data

1988-07-06 JP

Abstract

A trench dual-gate MOSFET comprises a projection which is bent to enclose a predetermined region on a semiconductor substrate of a first conductivity type. This projection is defined by a trench formed by selectively removing the surface region of the semiconductor substrate. A gate insulation film is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection. A gate electrode is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection, with the gate insulation film interposed and in a manner to surround the projection. A first impurity region of a second conductivity type, which serves as either a source or drain region, is formed in the top portion of the projection. A second impurity region of the second conductivity, which serves as either a drain or source region, is formed in the surface region of that portion of the semiconductor substrate which is located around the base of the projection.

Other References

Mizuno et al., "High Speed and Highly Reliable Trench MOSFET With Dual Gate", Symp. VLSI, pp. 23-24, 1988
V. L. Rideout., "Method for Fabricating an Enclosed DMOS Device", IBM Technical Disclosure Bulletin, vol. 21, No. 5, pp. 2105-2106, 1978
Richardson et al., "A Trench Transistor Cross-Point DRAM Cell," IEDM Technical Digest, pp. 714-719, 198