Programmable configurable logic memory
September 22, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRewritable programmable logic array Multiple-function programmable logic arrays Storage logic array having two conductor data column Semiconductor integrated circuit device Writable array logic Soft programmable logic array Writable logic array Semiconductor memory device using partial decoders for redundancy Power saving input buffer for use with a gate array Semiconductor fuse programmable array structure InventorsAssigneeApplicationNo. 411331 filed on 09/22/1989US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)326/38, Having details of setting or programming of interconnections or logic functions326/44, Field effect transistor365/225.7, Having fuse element708/232Array of elements (e.g., AND/OR array, etc.)ExaminersPrimary: Miller, Stanley D.Assistant: Bertelson, David R. Attorney, Agent or FirmInternational ClassesG11C 007/00H03K 019/096 H03K 019/003 H03K 003/01 AbstractA reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner. | |
