U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Data processing system incorporating a memory resident directive for synchronizing multiple tasks among plurality of processing elements by monitoring alternation of semaphore data

Patent 4965718 Issued on October 23, 1990. Estimated Expiration Date: Icon_subject September 29, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3879711

Program protection module for programmable controller
Patent #: 4118789
Issued on: 10/03/1978
Inventor: Casto ,   et al.

Extended semaphore architecture
Patent #: 4320451
Issued on: 03/16/1982
Inventor: Bachman ,   et al.

Data processing system having redundant control processors for fault detection
Patent #: 4456952
Issued on: 06/26/1984
Inventor: Mohrman ,   et al.

Parallel queueing method
Patent #: 4482956
Issued on: 11/13/1984
Inventor: Tallman

Circuit arrangement for inputting control signals into a microcomputer system
Patent #: 4488220
Issued on: 12/11/1984
Inventor: Friedli ,   et al.

Apparatus for invalidating the content of an instruction buffer by program store compare check
Patent #: 4500959
Issued on: 02/19/1985
Inventor: Kubo ,   et al.

Shared resource locking apparatus
Patent #: 4574350
Issued on: 03/04/1986
Inventor: Starr

Method and apparatus for a compare and swap instruction
Patent #: 4584640
Issued on: 04/22/1986
Inventor: MacGregor ,   et al.

Shared and exclusive access control
Patent #: 4604694
Issued on: 08/05/1986
Inventor: Hough

More ...

Inventors

Application

No. 250673 filed on 09/29/1988

US Classes:

718/104, Resource allocation711/156Status storage

Examiners

Primary: Lee, Thomas C.

Attorney, Agent or Firm

International Classes

G06F 009/46
G06F 011/30

Abstract

In a data processing system of the type including a plurality of processing elements interconnected with each other and with a plurality of memory elements by an interconnection means, a method is provided for accommodating the accessing of a selected memory location in a selected one of the memory elements by at least one requesting processing element to read data stored thereat. The method thereby permits the communication of information between the plurality of processing elements. The method comprising the steps of: sending, from the requesting processing element to the selected memory element via the interconnecting means, a directive including (1) the address of the selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending the directive; reading in the selected memory element the data stored at the selected memory location; comparing in the memory element the read data with the comparison value; notifying the requesting processing element via the interconnection means if the read data matches the comparison value; storing the directive in the selected memory element if the read data does not match the comparison value; and repeating the reading, comparing, and notifying steps each time the data in the selected memory location is altered.

Other References

  • "An Introduction to Processing Systems", H. M. Deitel, Addison Wesley Publishing Company, Inc., 1984, pp. 55-71
  • "Software Engineering with Ada", G. Booch, Benjamin/Cummings Publishing Co., 1983, pp. 231-235
  • IEEE Porceedings of the 1985 International Conference on Parallel Processing, pp. 772-781, "A Methodology for Predicting Multiprocessor Performance", by A. Norton et al
  • IEEE Proceedings of the 1985 International Conference on Parallel Processing, pp. 764-771, "The Research Parallel Processor Prototype (RP3): Introduction and Architecture", by G. F. Pfister et al
  • IEEE Proceedings of the 1985 International Conference on Parallel Processing, pp. 790-797, "`Hot Spot` Contention and Combining in Multistage Interconnection Networks", by G. F. Pfister et al
  • IEEE Proceedings of the 1986 International Conference on Parallel Processing, pp. 28-34, "The Onset of Hot Spot Contention", by M. Kumar et al
  • IEEE Proceedings of the 1985 International Conference on Parallel Processing, pp. 782-789, "RP3 Processing-Memory Element", by W. C. Brantley et al
  • "Computer Architecture and Parallel Processing", by Hwang and Griggs, McGraw-Hill, Inc., 1984, pp. 375-38
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