Semiconductor package with ground plane
Patent 4965654 Issued on October 23, 1990. Estimated Expiration Date: 
October 30, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 30, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPlastic package for high frequency semiconductor devices Peripheral/area wire bonding technique Means for reducing signal propagation losses in very large scale integrated circuits Package semiconductor chip Semiconductor package Patent #: 4916519 InventorsApplicationNo. 428533 filed on 10/30/1989US Classes:257/676, With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED)257/696, Bent (e.g., J-shaped) lead257/792, Including polyimide257/E23.036, Additional leads being wiring board (EPO)257/E23.039Chip-on-leads or leads-on-chip techniques, i.e., inner lead fingers being used as die pad (EPO)ExaminersPrimary: Hille, RolfAssistant: Clark, S. V. Attorney, Agent or FirmInternational ClassesH01L 023/48H01L 023/12 H01L 023/54 AbstractA plastic encapsulated semiconductor package in which the connecting lead frame members are deposited over the surface of the device together with a covering ground plane so as to provide enhanced electrical and thermal coupling of the members and the device and so reduce the signal to noise ratio by a factor or greater than three over that available in other similar plastic encapsulated packages while simultaneously improving the transfer of heat out of the package.In particular, a lead frame having a plurality of conductors is attached to a major active surface of a semiconductor chip via a ground plane which, in the preferred embodiment, is a multilayered structure containing an insulated integral, uniform ground plane positioned between the lead frame and the chip and adhesively and insulatively joined to both of them. Wires connect terminals on the major active surface of the semiconductor chip to the ground plane and to selective lead frame conductors. The lead frame, the ground plane structure, the semiconductor chip, and the wires which connect the semiconductor chip terminals to the ground plane and to selected lead frame conductors are encapsulated with a suitable insulating material to form a semiconductor module or package. | |
