Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits
January 19, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRaised source and drain igfet device fabrication Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps Selective epitaxy method for making filamentary pedestal transistor Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon Self-aligned buried channel fabrication process Processes for manufacturing insulated-gate semiconductor devices with integral shorts Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes Process for the self-alignment of a double polycrystalline silicon layer in an integrated circuit device through an oxidation process Forming chan-stops by selectively implanting impurity ions through field-oxide layer during later stage of MOS-device fabrication InventorAssigneeApplicationNo. 470445 filed on 01/19/1990US Classes:438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/288, Having insulated electrode (e.g., MOSFET, MOS diode)257/E21.131, Selective epilaxial growth, e.g., simultaneous deposition of mono- and non-mono semiconductor material (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)438/300Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)ExaminersPrimary: Hearn, Brian E.Assistant: McAndrews, Kevin Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/335Foreign Application Priority Data1984-07-19 ITAbstractThe method involves the formation above the substrate of regions of epitaxial type automatically aligned with the gate electrode and designed to form the source and drain regions of the transistor. These regions are doped by ion implantation using a comparatively low implantation energy such that the doping agent does not penetrate into the substrate. By providing the source and drain junctions on the surface of the substrate, rather than in the substrate, there are no lateral junction capacitances and the horizontal dimensions of the IGFET may be reduced, with the result that high response speeds and high integration densities are obtained.Other References
| |
