System for determining status of errors in a memory subsystem
December 21, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3814922 Error logging in semiconductor storage units Hard or soft cell failure differentiator Apparatus for detecting, correcting and logging single bit memory read errors Apparatus for detecting, correcting and logging single bit memory read errors using syndrome generating and decoding circuitry Apparatus for high speed fault mapping of large memories System for updating error map of fault tolerant memory Systematic memory error detection and correction apparatus and method Partial defective chip memory support system Remap method and apparatus for a memory system which uses partially good memory devices InventorsAssigneeApplicationNo. 287928 filed on 12/21/1988US Classes:714/764, Error correct and restore714/704, Error count or rate714/719, Read-in with read-out and compare714/723Error mapping or loggingExaminersPrimary: Smith, JerryAssistant: Beausoliel, Robert Attorney, Agent or FirmInternational ClassG06F 011/10AbstractA system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.Other References
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