Memory controller with error logging
December 21, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for detecting, correcting and logging single bit memory read errors Apparatus for detecting, correcting and logging single bit memory read errors using syndrome generating and decoding circuitry Fault alignment exclusion method to prevent realignment of previously paired memory defects Systematic memory error detection and correction apparatus and method Partial defective chip memory support system Remap method and apparatus for a memory system which uses partially good memory devices Apparatus for error correction Correction and monitoring of transient errors in a memory system Memory correction scheme using spare arrays Memory failure detection apparatus Patent #: 4809276 InventorsAssigneeApplicationNo. 287927 filed on 12/21/1988US Classes:714/764, Error correct and restore714/704, Error count or rate714/719, Read-in with read-out and compare714/723Error mapping or loggingExaminersPrimary: Smith, JerryAssistant: Beausoliel, Robert Attorney, Agent or FirmInternational ClassG06F 011/10AbstractIn accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred. | |
