Memory addressing arrangement
Patent 4964037 Issued on October 16, 1990. Estimated Expiration Date: 
October 16, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 16, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMemory controller with burst mode capability Multiwork memory data storage and addressing technique and apparatus Mass memory system addressing circuit Multi-user read-ahead memory Odd/even storage in cache memory Patent #: 4724518 InventorsAssigneeApplicationNo. 019898 filed on 02/27/1987US Classes:711/157InterleavingExaminersPrimary: Lall, Parshotam S.Assistant: Trans, V. N. Attorney, Agent or FirmInternational ClassG06F 013/00AbstractA memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded. | |
