U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Bus regulating system

Patent 4959775 Issued on September 25, 1990. Estimated Expiration Date: Icon_subject December 22, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

High speed bus architecture
Patent #: 4494192
Issued on: 01/15/1985
Inventor: Lew ,   et al.

Priority control apparatus for a bus in a bus control system having input/output devices
Patent #: 4583160
Issued on: 04/15/1986
Inventor: Iguma

Bus master capable of relinquishing bus on request and retrying bus cycle
Patent #: 4602327
Issued on: 07/22/1986
Inventor: LaViolette ,   et al.

Time multiplexed processor bus Patent #: 4630193
Issued on: 12/16/1986
Inventor: Kris

Inventor

Assignee

Application

No. 145751 filed on 12/22/1987

US Classes:

710/115Physical position bus prioritization

Examiners

Primary: Chan, Eddie P.

Attorney, Agent or Firm

International Classes

G06F 013/14
G06F 013/36

Foreign Application Priority Data

1986-05-29 JP

Abstract

A bus regulating system has a bus shared by a plurality of modules (10, 20, 30) and a bus usage permit signal line (4) in the form of a daisy chain. The usage of the bus is flexibly controlled according to the tasks of the modules (10, 20, 30). Each of the modules (10, 20, 30) has in its bus control circuit (12, 22, 32) overlapping request determining circuit and continued use determining circuit. The overlapping request determining circuit issues an overlapping request signal even if a request signal is issued from another module when a higher level task is being processed. The overlapping request determining circuit does not issue a request signal if a request signal is issued from another module when a lower level task is being processed. The continued use determining means continuously keeps the right to use the bus when a higher level task is being processed, and abandons the right to use the bus after the bus has been used when a lower level task is being processed.

Other References

  • Elektronische Rechen Anlagen, vol. 21, No. 4, Aug. 1979, "Multiprocessor System For the Real-Time Digital Processing of Video-Image Series", Nicolae et al. pp. 171-183
  • IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, "Prioritized Data Communication System Using a Common Bus", pp. 1555-1556
  • Wescon/79 Conference Record, San Francisco, CA, Sep. 18-20, 1979, Paper 28/1, "Multiprocessing With Single Board Computers--Hardware Considerations", by L. Soltesz, pp. 1-6
  • Proceedings of the Fall Joint Computer Conference, Araheim, California, Nov. 14-16, 1967, vol. 31, "Intercommunication of Processors and Memory", pp. 621-63
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