High speed bus architecture
Priority control apparatus for a bus in a bus control system having input/output devices
Bus master capable of relinquishing bus on request and retrying bus cycle
Time multiplexed processor bus Patent #: 4630193
ApplicationNo. 145751 filed on 12/22/1987
US Classes:710/115Physical position bus prioritization
ExaminersPrimary: Chan, Eddie P.
Attorney, Agent or Firm
International ClassesG06F 013/14
Foreign Application Priority Data1986-05-29 JP
AbstractA bus regulating system has a bus shared by a plurality of modules (10, 20, 30) and a bus usage permit signal line (4) in the form of a daisy chain. The usage of the bus is flexibly controlled according to the tasks of the modules (10, 20, 30). Each of the modules (10, 20, 30) has in its bus control circuit (12, 22, 32) overlapping request determining circuit and continued use determining circuit. The overlapping request determining circuit issues an overlapping request signal even if a request signal is issued from another module when a higher level task is being processed. The overlapping request determining circuit does not issue a request signal if a request signal is issued from another module when a lower level task is being processed. The continued use determining means continuously keeps the right to use the bus when a higher level task is being processed, and abandons the right to use the bus after the bus has been used when a lower level task is being processed.