Output controller for initiating delayed or conditional commands via a general purpose computer
Digital computer monitoring and restart circuit
Multiple source clock encoded communications error detection circuit
Arrangement for monitoring the function of a programmable electronic switching circuit
Dynamic self-checking safety circuit means
Dual input watchdog timer
Control device for a vehicle
Data transmission system adapted to facilitate detection of safe receipt of a transmitted data frame by a receiving station Patent #: 4558428
ApplicationNo. 562011 filed on 12/16/1983
US Classes:714/55, Timing error (e.g., watchdog timer time-out)713/502, Counting, scheduling, or event timing714/23Resetting processor
ExaminersPrimary: Clark, David L.
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 001/24
Foreign Application Priority Data1982-12-21 JP
AbstractA watchdog timer works in concert with special computer program features to monitor program execution and reset the computer in case of malfunction. The computer CPU is programmed to periodically output one of an alternating pair of values to a register which holds the value for a comparator. The output value is compared to a predetermined value equal to one of the alternating output value. When the compared values are equal, the comparator outputs a reset signal to a counter. The counter counts clock pulses and if it counts to its full capacity before being reset by the comparator output, it outputs a reset signal which causes the computer to restart program execution. A second comparator may be provided to compare the alternating values to a reference value equal to the other values. Thus the comparators check for proper output of both signals and reset the counter only in response to receipt of both values. In addition a second counting system may be provided so that the computer will be reset whether the period of alternating value output increases or decreases.