Integrated telecommunication system with improved digital voice response
Patent 4955054 Issued on September 4, 1990. Estimated Expiration Date: 
October 5, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 5, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable feature card Speech response interface circuit Digital switching system Full service voice/data system Cellular mobile radio service telephone system Resource allocation in distributed control systems Communications switching system Patent #: 4791639 InventorsAssigneeApplicationNo. 253470 filed on 10/05/1988US Classes:379/269, Distributed control370/360, Switching control379/88.28Solid state memory storageExaminersPrimary: Brown, Thomas W.Attorney, Agent or FirmForeign Patent References
International ClassesH04M 003/50H04Q 011/04 AbstractAn integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross-point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.Other References
Field of SearchDistributed control | |
