U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method and apparatus for asymmetrical RLL coding

Patent 4949196 Issued on August 14, 1990. Estimated Expiration Date: Icon_subject March 30, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3394352

3685033

3689899

3840854

Apparatus and method for generating a data code with a spectral null
Patent #: 4028535
Issued on: 06/07/1977
Inventor: Franaszek, et al.

Sequential encoding and decoding of variable word length, fixed rate data codes
Patent #: 4115768
Issued on: 09/19/1978
Inventor: Eggenberger ,   et al.

Data encoding method and system employing two-thirds code rate with full word look-ahead
Patent #: 4337458
Issued on: 06/29/1982
Inventor: Cohn ,   et al.

Videodisc player with constant turntable velocity
Patent #: 4338683
Issued on: 07/06/1982
Inventor: Furukawa ,   et al.

Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3
Patent #: 4413251
Issued on: 11/01/1983
Inventor: Adler ,   et al.

Run length limited data encoder
Patent #: 4484176
Issued on: 11/20/1984
Inventor: Fitzpatrick

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Inventors

Application

No. 175171 filed on 03/30/1988

US Classes:

360/40, In specific code or form341/59To or from run length limited codes

Examiners

Primary: Canney, Vincent P.

Attorney, Agent or Firm

Foreign Patent References

  • 0070387 EP. 06/13/1982
  • 0083412 EP. 11/13/1982
  • 0155529 EP. 02/13/1985

International Classes

G11B 005/09
H03K 013/24

Abstract

This disclosure concerns for generating asymmetrically constrained run-length-limited encoded data from a serialized binary string of 1's and 0's. The method comprises the steps of encoding the input data bits using a run-length-limited constraint in the form of M/N (d,k), where M is the number of input data bits, N is the number of output bits associated therewith, d is the minimum number of 0 data bits between adjacent data bit 1's, and k is the maximum number of 0 data bits between adjacent 1's; and alternating the values of d and k between a set (d1, k1) and a set (d2, k2), respectively, where d1 ≠d2. The apparatus comprises means for generating N output data bits in response to M input data bits and for generating data bit 0's between data bit 1's based upon a run-length-limited coding constraints (d1, k1) and (d2, k2), where constraints (d1, k1) and (d2, k2) apply alternately to runs of zeroes between output data ones. Fractional numerical values of d1 and d2 can be employed in the method or apparatus.

Other References

  • Digital Modulation System, Patent Abstracts of Japan, vol. 9, No. 244 (E-346) [1967], Sep. 30, 1985
  • IBM Technical Disclosure Bulletin, vol. 28, No. 3, Aug. 1985
  • "Algorithms for Sliding Block Codes", An Application of Symbolic Dynamics to Information Theory, by Roy Adler et al., vol. IT-29, No. 1, Jan. 1983, pp. 5-2
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