Process for elevated source/drain field effect structure
May 22, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3912557 CMOS process Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate Self-aligned metal process for field effect transistor integrated circuits Method for making semiconductor device having improved thermal stress characteristics Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Method of manufacturing semiconductor device Fabrication technique for integrated circuits Selective titanium silicide formation Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies InventorsAssigneeApplicationNo. 353933 filed on 05/22/1989US Classes:438/290, After formation of source or drain regions and gate electrode257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)438/303, Utilizing gate sidewall structure438/305Plural doping stepsExaminersPrimary: Hearn, Brian E.Assistant: Thomas, T. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/336AbstractA process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.Other References
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