Method of manufacturing a semiconductor device
Patent 4948743 Issued on August 14, 1990. Estimated Expiration Date: 
June 29, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 29, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3825442 Manufacturing a low voltage n-channel MOSFET device Contact vias in semiconductor devices Patent #: 4733291 InventorAssigneeApplicationNo. 373102 filed on 06/29/1989US Classes:438/701, Tapered configuration257/E21.578, Tapered via holes (EPO)438/586, Combined with formation of ohmic contact to semiconductor region438/760Utilizing reflow (e.g., planarization, etc.)ExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/31H01L 021/88 Foreign Application Priority Data1988-06-29 JPAbstractA method of manufacturing a semiconductor device, includes the following steps: part of an insulation film is left on the bottom of a contact hole of the insulation film formed on a semiconductor substrate or a separate insulation film is otherwise formed, under which condition a satisfactory slope is formed on the peripheral edge and the side wall of the contact hold by providing the semiconductor substrate with a heat treatment. According to the present invention, it is possible thereafter to improve the step coverage of a metal interconnection to be formed on the surface of the insulation film and to prevent breakage of the metal interconnection, thereby substantially improving the reliability of the resulting semiconductor device. | |
