Sample-and-hold digital phase-locked loop for ask signals
August 8, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFast synchronization circuit for phase locked looped decoder Modem multiplexer synchronization by radial modulation QAM Demodulator carrier recovery loop using n-m LSB's Circuit for establishing accurate sample timing System and method for transporting data Multiple quadrature-phase amplitude modulating system capable of reducing a peak amplitude Decision timing control circuit Signal processing system Patent #: 4805189 InventorAssigneeApplicationNo. 391215 filed on 08/08/1989US Classes:375/340, Particular pulse demodulator or detector329/347, AMPLITUDE MODULATION DEMODULATOR375/268, Amplitude modulation607/32Communicating with pacer (e.g., telemetry)ExaminersPrimary: Olms, Douglas W.Assistant: Chin, Stephen Attorney, Agent or FirmInternational ClassH03D 001/00AbstractA digital phase-locked looped generates a clock signal synchronized with a carrier signal modulated by amplitude shift keying (ASK). During periods when no carrier signal is present, the generated clock signal coasts at the frequency of the carrier signal most recently present, rather than trying to phase-lock on noise. A binary controlled digital oscillator generates the clock signal. A phase detector determines the difference between the phase of the carrier signal, when present, and the local clock signal. When the average amplitude of the carrier signal exceeds a prescribed threshold level, the phase detector output is sampled and passed to an integrator circuit, where the phase difference is integrated. The output of the integrator circuit is applied to a pulse generator, causing the pulse generator's duty cycle to change proportionally. In turn, the pulses are applied to the binary controlled digital oscillator, causing the frequency of the local clock signal to shift in a direction that minimizes the phase error between the local clock signal and the carrier signal. When the average amplitude of the carrier signal is less than the prescribed threshold level, the phase detector output is not smapled. In such case, the output of the integrator circuit remains at the value obtained from the most recent prior phase detector sample.Other References
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