Patent ReferencesExtended drain self-aligned silicon gate MOSFET Method of manufacturing submicron channel transistors Sidewall channel stop process Patent #: 4753896 InventorsAssigneeApplicationNo. 435135 filed on 11/09/1989US Classes:438/154, Complementary field effect transistors257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)257/E29.281, For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)438/231, Plural doping steps438/303Utilizing gate sidewall structureExaminersPrimary: Hearn, Brian E.Assistant: Quach, T. N. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/336AbstractA process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional photolithographic or implant steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions and the associated implants can be used in the formation of the contact region. | |