Adder for exponent arithmetic
Method and a means for checking normalizing operations in a computer device
Floating-point adder circuit
Floating-point data rounding and normalizing circuit Patent #: 4779220
ApplicationNo. 364478 filed on 06/12/1989
US Classes:708/530, Error detection or correction708/525, Status condition/flag generation or use708/551Round off or truncation
ExaminersPrimary: Harkcom, Gary V.
Assistant: Mai, Tan V.
Attorney, Agent or Firm
International ClassG06F 011/00
Foreign Application Priority Data1988-06-10 JP
AbstractAn overflow correction circuit is coupled to receive an output of an arithmetic operation circuit having first and second data inputs. The first data input is connected to an internal data bus so as to receive data to be subjected to an arithmetic operation, and the output of the arithmetic operation circuit outputs a result of arithmetic operation. The overflow correction circuit comprises a selector having a first input connected to receive the result of arithmetic operation from the arithmetic operation circuit and a second input and an output, a corrected value generating circuit having an output connected to the second input of the first selector, an overflow detection circuit coupled to receive the output of the arithmetic operation circuit and for generating an overflow signal indicative of whether or not there occurs an overflow in the result of the arithmetic operation. The first overflow signal is supplied to the selector so as to control the first selector in such a manner that when the overflow signal does not indicate occurrence of the overflow, the selector outputs the output of the arithmetic operation circuit as its output and when the overflow signal indicates occurrence of the overflow, the selector outputs the output of the corrected value generating circuit as its output. There is provided an accumulator having an input connected to receive the output of the first selector and an output connected to the second data input of the arithmetic operation circuit.