Method of making cmos with shallow source and drain junctions
January 24, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-aligned metal process for field effect transistor integrated circuits Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Self-aligned field effect transistor process Fabrication of MOS integrated circuit devices Fabrication of FETs Method of manufacturing semiconductor device Method of fabricating bipolar transistors and insulated gate field effect transistors having doped polycrystalline silicon conductors Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate Grown side-wall silicided source/drain self-align CMOS fabrication process Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate InventorAssigneeApplicationNo. 301073 filed on 01/24/1989US Classes:438/224, Plural wells257/371, Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells257/374, Dielectric isolation means (e.g., dielectric layer in vertical grooves)257/377, With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)257/742, With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal)257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)438/229, Self-aligned438/301, Source or drain doping438/586Combined with formation of ohmic contact to semiconductor regionExaminersPrimary: Hearn, Brian E.Assistant: Wilczewski, Mary Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/235AbstractA CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.Other References
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