Method of fabricating an insulated gate semiconductor device having a self-aligned gate
March 23, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-aligned metal process for field effect transistor integrated circuits Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Production of Schottky barrier diode Self-aligned field effect transistor process Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Method for making Schottky diode having limited area self-aligned guard ring Patent #: 4691435 InventorAssigneeApplicationNo. 172029 filed on 03/23/1988US Classes:438/227, Having well structure of opposite conductivity type257/369, Complementary insulated gate field effect transistors257/387, Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.432, With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)257/E27.062, Complementary MIS (EPO)257/E29.122, Characterized by relative position of source or drain electrode and gate electrode (EPO)257/E29.135, Characterized by length or sectional shape (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/229, Self-aligned438/232, Plural doping steps438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/301, Source or drain doping438/307Using same conductivity-type dopantExaminersPrimary: Hearn, Brian E.Assistant: Wilczewski, M. Attorney, Agent or FirmInternational ClassesH01L 021/265H01L 021/283 Foreign Application Priority Data1987-03-25 JPAbstractThe present invention provides a fabrication method of miniature insulated gate semiconductor devices such as MOS and CMOS in which their gates are formed by self-alignment, and in addition, provision of lightly doped drain (LDD) structure is easy. Therefore the present invention is extremely effective in the fabrication of miniature semiconductor devices which can be highly integrated and can operate at high speed.Other References
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